1. Field of the Invention
The present invention relates to a delay circuit and a semiconductor memory device, and more particularly to a delay circuit that is applied to a semiconductor device having an auto power-down function.
2. Description of the Related Art
With increasing functional complexity in various kinds of circuits in recent years, it has come to be widely practiced to supply signals by delaying signal timing. This trend has brought a need for a delay circuit which can change its delay time, requires fewer components, and consumes less current, and which can output a delayed signal without being affected by noise or by fluctuations in supply power.
Namely, in the prior art, a delay circuit (CR delay circuit) comprises, for example, a resistor, a capacitor, and an inverter. Note that, the voltage change of the input signal is slowed by a time constant (T=CR) of the resistor and capacitor, thereby delaying the timing at which the input voltage to the inverter at the next stage exceeds the threshold voltage of the inverter. In this way, an output signal, which is delayed with respect to the input signal of the delay circuit, can be obtained.
However, in the prior art delay circuit, the input voltage of the inverter is determined only by the time constant of the resistor and capacitor, and thus the change of the voltage is still slow after the threshold voltage is exceeded. Therefore, if the input voltage fluctuates, and if the input voltage of the inverter drops again below the threshold voltage, an unwanted pulse may be included in the output signal.
The prior art delay circuit and problems associated with the prior art delay circuit will be described in detail later with reference to drawings.